NOII4SM6600A - 6.6 Megapixel CMOS Image Sensor

1 DATA Semiconductor Components Industries, LLC, 2014 August, 2021 Rev. 161 Publication Order Number:NOII4SM6600 Megapixel cmos ImageSensorNOII4SM6600 AFeatures 2210 (H) x 3002 (V) Active Pixels mm x mm Square Pixels 1 inch Optical Format Monochrome Output Frame Rate: 5 fps for Active Window of 2210 x 3002 89 fps for Active Window of 640 x 480 High Dynamic Range Modes: Double Slope, Non DestructiveRead out (NDR) Electronic Rolling Shutter Master Clock: 40 MHz Single V Supply V Supply for Extended Dynamic Range 30 C to +65 C Operational Temperature Range 68-Pin LCC Package Power Dissipation: 225 mW These Devices are Pb Free and are RoHS CompliantApplications Machine Vision Biometry Document ScanningDescriptionThe IBIS4-6600 is a solid-state cmos Image Sensor that integrates complete analog Image acquisition, and a digitizer anddigital signal processing system on a single chip.

2 This Image Sensor has a resolution of MPixel with 2210 x 3002 activepixels. The Image size is fully programmable for user-defined windows. The pixels are on a mm user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digitalzoom. Subsampling reduces resolution while maintaining the constant field of view. The analog video output of the pixelarray is processed by an on-chip analog signal pipeline. Double Sampling (DS) eliminates the fixed pattern programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit ADC converts theanalog data to a 10-bit digital word stream. The Sensor uses a three-wire Serial-Parallel (SPI) interface. It operates with asingle V power supply and requires only one master clock for operation up to 40 MHz.

3 It is housed in a 68-pin ceramicLCC data sheet enables the development of a camera system, based on the described timing and interfacing given in thefollowing INFORMATIONM arketing Part NumberDescriptionPackageNOII4SM6600A-QDC Mono with Glass68 pin LCCNOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 1. IBIS4 6600 Image SPECIFICATIONSP arameterSpecificationRemarksPixel Architecture3T-PixelPixel mm x mmThe resolution and pixel size results in a mm x mmoptical active x 3002 Pixel Rate40 MHzUsing a 40 MHz system clock and 1 or 2 parallel outputsShutter TypeElectronic Rolling ShutterFull Frame Rate5 frames/secondIncreases with ROI read out and/or subsamplingELECTRO OPTICAL SPECIFICATIONSP arameterSpecificationRemarksFPN (local)< , 2 LSB10%RMS of saturation signalPRNU (local)< of signal levelConversion Gain43 mV/e-At output (measured)Output Signal VAt nominal conditionsSaturation Charge21500 e-Sensitivity (peak)411 650 nm(85 lux = 1 W/m2)Sensitivity (visible)328 nm(163 lux = 1 W/m2)Peak QE * FFPeak Spectral Response25% A/WAverage QE*FF = 22% (visible range)

4 Average SR*FF = A/W (visible range)See the section Spectral Response Curve on page Factor35%Light sensitive part of pixel (measured)Dark mV/s78 e-/sTypical value of average dark current of the whole pixel array(at 21 C)Dark Signal Non mV/s191 e-/sDark current RMS value (at 21 C)Temporal Noise24 RMS e-Measured at digital output (in the dark)Signal/Noise Ratio895:1 (40 dB)Measured at digital output (in the dark)Dynamic Range59 dBSpectral Sensitivity Range400 - 1000 nmOptical Cross Talk15%4%To the first neighboring pixelTo the second neighboring pixelPower Dissipation225 mWTypical (including ADCs) Response 500 600 700 800 900 1000 Wavelenght [nm]Spectral response [A/W]QE 10%QE 20%QE 30%Figure 2. Spectral Response CurveFigure 2 shows the characteristics of the spectral curve is measured directly on the pixels.

5 It includes theeffects of nonsensitive areas in the pixel, for example,interconnection lines. The Sensor is light sensitive between400 and 1000 nm. The peak QE x FF is 25% approximately650 nm. In view of a fill factor of 35%, the QE is close to70% between 500 and 700 Voltaic Response CurveFigure 3. Electro Voltaic Response # electronsOutput swing [V]500010000150002000025000 Figure 3 shows the pixel response curve in linear responsemode. This curve is the relation between the electronsdetected in the pixel and the output signal. The resultingvoltage-electron curve is independent of any parameters, forexample, integration time. The voltage to electronsconversion gain is 43 1. FEATURES AND GENERAL SPECIFICATIONSF eatureSpecification/DescriptionElectroni c shutter typeRolling shutterIntegration time control60 ms - 1/frame periodWindowing (ROI)Randomly programmable ROI read outSub Sampling ModesSeveral sub sample modes can be programmed (refer Table 8 on page 12)Extended Dynamic RangeDual slope (up to 90 dB optical dynamic range) and nondestructive read out modeAnalog OutputThe output rate of 40 Mpixels/s can be achieved with two analog outputs, each working at20 Mpixel/sDigital OutputTwo on-chip 10-bit ADCs at 20 Msamples/s are multiplexed to one digital 10-bit output at40 Msamples/sSupply Voltage VDDN ominal V (some supplies require V for extended dynamic range)Logic VInterfaceSerial Peripheral Interface (SPI)Package68-pin SpecificationsTable 2.

6 RECOMMENDED OPERATING RATINGS (Notes 1 and 3)SymbolDescriptionMinMaxUnitsTJOperatin g temperature range-3065 CTable 3. ABSOLUTE MAXIMUM RATINGS (Notes 2, 3 and 4)SymbolParameterMinMaxUnitsVDD (Note 5)DC Supply Voltage Input Voltage (VDD + )VVOUTDC Output Voltage (VDD + )VTS (Note 3)Storage Temperature 30+85 C%RHHumidity (Relative)-85% at 85 CElectrostatic discharge (ESD)Human Body Model (HBM)(Note 3)VCharged Device Model (CDM)LULatch-up(Note 4)mA1. Operating ratings are conditions in which operation of the device is intended to be functional. All parameters are characterized for DCconditions after thermal equilibrium is established. Unused inputs must always be tied to an appropriate logic level, for example, VDD or Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degradedevice reliability.

7 These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specifiedis not This device does NOT contain circuitry to protect the inputs against damage caused by high static voltages or electric fields. onsemirecommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625 A. Refer to Application The IBIS4 6600 does not have latchup VDD = VDDD = VDDA (VDDD is supply to digital circuit, VDDA to analog circuit).All parameters are characterized for DC conditions afterthermal equilibrium is established. Unused inputs mustalways be tied to an appropriate logic level, for example,VDD or GND. The IBIS4-6600 is extremely susceptible tonoise on the power supplies. In addition, it has no powersupply filtering on chip.

8 Therefore, all power supplies to thesensor must be clean with the target being to achieve a lownoise (1 mV). Special attention must be given to the pixelsupplies VPIX, GND_AB, VRESET and 4. RECOMMENDED DC OPERATING CONDITIONSP arameterDescriptionTypicalDynamicCurrent sMinTyp (V)MaxVDD_PIXVDD of pixel core-5% V5%VDD_RESETR eset voltage. Highest voltage to the chip. forextended dynamic range or hard reset -5% VVDD_RESET_DSVariable reset voltage (dual slope)-5% V5%VDDAVDD of analog supply3 mA-5% V5%VDDA_ADCA nalog supply to the ADC53 mA-5% V5%VDDAMPVDD of analog output. (Can be connected to VDDA)20 mA-5% V5%VDDDVDD of digital supply3 mA-5% V5%VDDD_ADCD igital supply to the ADC10 mA-5% V5% ARCHITECTUREF loor Planre s e tselectanalog output(2)eos _yleos _yrtr i ltr i rDAC inADC , 10 bitADC , 10 bitsequencerIMAGE CORESENSORSPI pixel arrayaddres s able x shift register + sub s amplingaddres s able y s hift regis ter + s ub s amplingcolumn amplifiersre s e t a nd s e le c t drive rsre s e t a nd s e le c t drive rsclk_ysync_ylPixel (0,0)DACaddressable y shift register + sub samplingclk_yrsync_yD ig.

9 LogicDig. logicaddress & da ta busFigure 4. Floor Plan2210 x 3002(excl. dark +dummy pixels)Figure 4 shows the architecture of the designed imagesensor. It consists of the pixel array, shift registers for thereadout in x and y direction, parallel analog outputamplifiers, and column amplifiers that correct for the fixedpattern noise caused by threshold voltage out the pixel array starts by applying a y clock pulseto select a new row, followed by a calibration sequence tocalibrate the column amplifiers (row blanking time).Depending on external bias resistors and timing, typicallythis sequence takes about seven seconds every line(baseline). This sequence is necessary to remove the FixedPattern Noise of the pixel and of the column amplifiersthemselves (by a Double Sampling technique).

10 Pixels canalso be read out in a nondestructive DACs are added to make the offset level of the pixelvalues adjustable and equal for the two output buses. A thirdDAC is used to connect the buses to a stable voltage duringthe row blanking period, or reset the buses continuously incase of a nondestructive 10-bit ADCs running at 20 Msamples/s convert theanalog pixel values. The digital outputs are multiplexed toone digital 10-bit output at 40 Msamples/s. Note that theseblocks are electrically completely isolated from the sensorpart, except for the multiplexer, for which the settings areuploaded through the shared address and data x and y shift registers have a programmable startingpoint. The possibilities of the starting point are limitedbecause of limitations imposed by subsamplingrequirements.