Analog Multiplexers/ Demultiplexers

1 Semiconductor Components Industries, LLC, 2017 July, 2021 Rev. 121 Publication Order Number:MC74HC4051A/DAnalog Multiplexers/ DemultiplexersHigh Performance Silicon Gate CMOSMC74HC4051A,MC74HC4052A,MC74HC4053 AThe MC74HC4051A, MC74HC4052A and MC74HC4053A utilizesilicon gate CMOS technology to achieve fast propagation delays,low ON resistances, and low OFF leakage currents. These analogmultiplexers/ Demultiplexers control Analog voltages that may varyacross the complete power supply range (from VCC to VEE).The HC4051A, HC4052A and HC4053A are identical in pinout tothe metal gate MC14051AB, MC14052AB and MC14053AB. TheChannel Select inputs determine which one of the AnalogInputs/Outputs is to be connected, by means of an Analog switch , to theCommon Output/Input. When the Enable pin is HIGH, all analogswitches are turned Channel Select and Enable inputs are compatible with standardCMOS outputs; with pullup resistors they are compatible with devices have been designed so that the ON resistance (Ron) ismore linear over input voltage than Ron of metal gate CMOS a multiplexer / demultiplexer with injection current protection,see HC4851A and Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC VEE) = to V Digital (Control) Power Supply Range (VCC GND) = to V Improved Linearity and Lower ON Resistance Than Metal GateCounterparts Low Noise In Compliance with the Requirements of JEDEC Standard No.

2 7A Chip Complexity: HC4051A 184 FETs or 46 Equivalent GatesHC4052A 168 FETs or 42 Equivalent GatesHC4053A 156 FETs or 39 Equivalent Gates NLV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC Q100 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantThis document contains information on some products that are still under Semiconductor reserves the right to change or discontinue these products DIAGRAMSSOIC 16 TSSOP 16116HC405xAGAWLYWWHC405xAALYWGG116 SOIC 16 WIDE116HC405xAAWLYWWGSee detailed ordering and shipping information on page 13 ofthis data INFORMATIONx= 1, 2 or 3A= Assembly LocationWL, L= Wafer LotYY, Y= YearWW, W = Work WeekG or G= Pb Free Package(Note: Microdot may be in either location)SOIC 16D SUFFIXCASE 751 BTSSOP 16DT SUFFIXCASE 948 FSOIC 16 WIDEDW SUFFIXCASE 751G4051 ALYWGGQFN161 QFN16MN SUFFIXCASE 485 AWMC74HC4051A, MC74HC4052A, DIAGRAMMC74HC4051 ASingle Pole, 8 Position Plus Common OffX013X114X215X312X41X55X62X74A11B10C9 ENABLE6 multiplexer /DEMULTIPLEXERX3 ANALOGINPUTS/CHANNELINPUTSPIN 16 = VCCPIN 7 = VEEPIN 8 = GNDCOMMONOUTPUT/INPUT1516141312111021345 67 VCC98X2X1X0X3 ABCX4X6XX7X5 Enable VEEGNDP inout.

3 MC74HC4051A (Top View)OUTPUTSSELECTLLLLHHHHXLLHHLLHHXLHLH LHLHXFUNCTION TABLE MC74HC4051 AControl InputsON ChannelsEnableSelectCBAX0X1X2X3X4X5X6X7 NONELLLLLLLLHX = Don t CareLOGIC DIAGRAMMC74HC4052 ADouble Pole, 4 Position Plus Common OffX012X114X215X311Y01Y15Y22Y34A10B9 ENABLE6X SWITCHY SWITCHX13 ANALOGINPUTS/OUTPUTSCHANNEL SELECTINPUTSPIN 16 = VCCPIN 7 = VEEPIN 8 = GNDCOMMONOUTPUTS/INPUTSLLHHXLHLHXFUNCTIO N TABLE MC74HC4052 AControl InputsON ChannelsEnableSelectBAX0X1X2X3 LLLLHX = Don t CarePinout: MC74HC4052A (Top View)151614131211102134567 VCC98X2X1XX0X3 ABY0Y2YY3Y1 Enable VEEGNDY3Y0Y1Y2Y3 NONEMC74HC4051A, MC74HC4052A, DIAGRAMMC74HC4053 ATriple single Pole, Double Position Plus Common OffX012X113A11B10C9 ENABLE6X SWITCHY SWITCHX14 ANALOGINPUTS/OUTPUTSCHANNEL SELECTINPUTSPIN 16 = VCCPIN 7 = VEEPIN 8 = GNDCOMMONOUTPUTS/INPUTSLLLLHHHHXLLHHLLHH XLHLHLHLHXFUNCTION TABLE MC74HC4053 AControl InputsON ChannelsEnableSelectCBALLLLLLLLHX = Don t CarePinout: MC74HC4053A (Top View)151614131211102134567 VCC98 YXX1X0 ABCY1Y0Z1ZZ0 Enable VEEGNDZ0Z0Z0Z0Z1Z1Z1Z1Y0Y0Y1Y1Y0Y0Y1Y1X0 X1X0X1X0X1X0X1 NONEY02Y11Y15Z05Z13Z4Z SWITCHNOTE.

4 This device allows independent control of each Select Input A controls the X switch , Input B controlsthe Y switch and Input C controls the Z SwitchMAXIMUM RATINGSS ymbolParameterValueUnitVCCP ositive DC Supply Voltage(Referenced to GND)(Referenced to VEE) to + to + DC Supply Voltage (Referenced to GND) to + Input VoltageVEE toVCC + Input Voltage (Referenced to GND) to VCC + Current, Into or Out of Any Pin 25mAPDP ower Dissipation in Still Air,SOIC Package TSSOP Package 500450mWTstgStorage Temperature Range 65 to +150_CTLLead Temperature, 1 mm from Case for 10 SecondsSOIC or TSSOP Package260_CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any ofthese limits are exceeded, device functionality should not be assumed, damage may occur andreliability may be affected. Derating: SOIC Package: 7 mW/_C from 65_ to 125_CTSSOP Package: mW/_C from 65_ to 125_CThis device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields.

5 However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v inputs must always betied to an appropriate logic voltagelevel ( , either GND or VCC).Unused outputs must be left , MC74HC4052A, OPERATING CONDITIONSS ymbolParameterMinMaxUnitVCCP ositive DC Supply Voltage(Referenced to GND)(Referenced to VEE) DC Supply Voltage, Output (Referenced to GND) Input VoltageVEEVCCVVinDigital Input Voltage (Referenced to GND)GNDVCCVVIO*Static or Dynamic Voltage Across Temperature Range, All Package Types 55+125_Ctr, tfInput Rise/Fall TimeVCC = V(Channel Select or Enable Inputs)VCC = VVCC = VVCC = V00001000600500400nsFunctional operation above the stresses listed in the Recommended Operating Ranges is not implied.

6 Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.*For voltage drops across switch greater than V ( switch on), excessive VCC current may be drawn; , the current out of the switch maycontain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where NotedSymbolParameterConditionVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CVIHM inimum High Level Input Voltage,Channel Select or Enable InputsRon = Per Low Level Input Voltage,Channel Select or Enable InputsRon = Per Input Leakage Current,Channel Select or Enable InputsVin = VCC or GND,VEE = Quiescent SupplyCurrent (per Package)Channel Select, Enable andVIS = VCC or GND;VEE = GNDVIO = 0 VVEE = , MC74HC4052A, CHARACTERISTICS Analog SectionSymbolParameterConditionVCCVEEG uaranteed LimitUnit 55 to 25 C 85 C 125 CRonMaximum ON ResistanceVin = VIL or VIH; VIS = VCC toVEE; IS mA(Figures 1, 2) = VIL or VIH; VIS = VCC orVEE (Endpoints).

7 IS mA(Figures 1, 2) Difference in ON Resistance Between Any TwoChannels in the Same PackageVin = VIL or VIH;VIS = 1/2 (VCC VEE);IS Off Channel LeakageCurrent, Any One ChannelVin = VIL or VIH;VIO = VCC VEE; switch Off (Figure 3) Off ChannelHC4051 ALeakage Current,HC4052 ACommon ChannelHC4053 AVin = VIL or VIH;VIO = VCC VEE; switch Off (Figure 4) On ChannelHC4051 ALeakage Current,HC4052 AChannel to ChannelHC4053 AVin = VIL or VIH; switch to switch =VCC VEE; (Figure 5) CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)SymbolParameterVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CtPLH,tPHLM aximum Propagation Delay, Channel Select to Analog Output(Figure 9) ,tPHLM aximum Propagation Delay, Analog Input to Analog Output(Figure 10) ,tPHZM aximum Propagation Delay, Enable to Analog Output(Figure 11) ,tPZHM aximum Propagation Delay, Enable to Analog Output(Figure 11) Input Capacitance, Channel Select or Enable Inputs101010pFCI/OMaximum CapacitanceAnalog I/O353535pF(All Switches Off)Common O/I: HC4051 AHC4052 AHC4053A130805013080501308050 Feed Dissipation Capacitance (Figure 13)*HC4051 AHC4052 AHC4053 ATypical @ 25 C, VCC = V, VEE = 0 VpF458045* Used to determine the no load dynamic power consumption.

8 PD = CPD VCC2f + ICC , MC74HC4052A, APPLICATION CHARACTERISTICS (GND = 0 V)SymbolParameterConditionVCCVVEEV Limit*Unit25 CBWM aximum On Channel Bandwidthor Minimum Frequency Response(Figure 6)fin = 1 MHz Sine Wave; Adjust fin Voltageto Obtain 0dBm at VOS; Increase finFrequency Until dB Meter Reads 3dB;RL = 50W, CL = 51 52 53 MHz808080959595120120120 Off Channel Feed throughIsolation (Figure 7)fin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VISfin = 10kHz, RL = 600W, CL = 50 50 50dBfin = , RL = 50W, CL = 40 40 40 Feedthrough Select Input to CommonI/O (Figure 8)Vin 1 MHz Square Wave (tr = tf = 6ns);Adjust RL at Setup so that IS = 0A; Enable = GNDRL = 600W, CL = = 10kW, CL = Crosstalk Between Any TwoSwitches (Figure 12)(Test does not apply to HC4051A)fin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VISfin = 10kHz, RL = 600W, CL = 50 50 50dBfin = , RL = 50W, CL = 60 60 60 THDT otal Harmonic Distortion(Figure 14)fin = 1kHz, RL = 10kW, CL = 50pFTHD = THDmeasured THDsourceVIS = sine waveVIS = sine waveVIS = sine *Limits not tested.

9 Determined by design and verified by 1a. Typical On Resistance, VCC VEE = VFigure 1b. Typical On Resistance, VCC VEE = , INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS) , INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS)25 C- 55 C125 C25 C- 55 C125 , MC74HC4052A, 1c. Typical On Resistance, VCC VEE = VFigure 1d. Typical On Resistance, VCC VEE = , INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS) , INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS)20025 C- 55 C125 C25 C- 55 C125 1e. Typical On Resistance, VCC VEE = V017060504030 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS)2010234 5678925 C- 55 C125 C800 Figure 1f. Typical On Resistance, VCC VEE = V0160504030 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEERon, ON RESISTANCE (OHMS)20102348910111225 C- 55 C125 C0576 Figure 2.

10 On Resistance Test Set UpPLOTTERMINI COMPUTERPROGRAMMABLEPOWERSUPPLYDC ANALYZERVCCDEVICEUNDER TEST+-VEEANALOG INCOMMON OUTGNDMC74HC4051A, MC74HC4052A, 3. Maximum Off Channel Leakage Current,Any One Channel, Test Set UpFigure 4. Maximum Off Channel Leakage Current,Common Channel, Test Set UpFigure 5. Maximum On Channel Leakage Current,Channel to Channel, Test Set UpFigure 6. Maximum On Channel Bandwidth,Test Set UpFigure 7. Off Channel Feedthrough Isolation,Test Set UpFigure 8. Feedthrough Noise, Channel Select toCommon Out, Test Set UpOFFOFF67816 COMMON O/IVCCVEEVIHNCAVCCVEEVCCOFFOFF67816 COMMON O/IVCCVEEVIHANALOG I/OVCCVEEVCCONOFF67816 COMMON O/IVCCVEEVILVCCVEEVCCN/CAANALOG *finRLdBMETER*Includes all probe and jig *finRLdBMETER*Includes all probe and jig capacitanceVOSVOSRLVISVIL or VIHCHANNEL SELECTON/OFF67816 VCCVEECL*RL*Includes all probe and jig capacitanceCHANNEL SELECTTESTPOINTCOMMON O/I11 VCCOFF/ONANALOG I/ORLRLVCCGNDVin 1 MHztr = tf = 6 nsMC74HC4051A, MC74HC4052A, 9a.