AND9957 - On Board Charger (OBC) Three-phase PFC …

1 APPLICATION Semiconductor Components Industries, LLC, 2019 August, 2021 Rev. 31 Publication Order Number: AND9957 /DOn Board Charger (OBC) Three-phase PFC ConverterAND9957/DSummaryWith the coming electrification of the automotive market, the needof battery chargers is more and more demanded. With the simpleequation more power, shorter the recharge time is, a 3 phase supply ishere considered which can provide up to 3x the power ofa single phase 3 phase PFC Board here proposed is an example of the firststage of an On Board Charger system based on silicon carbideMOSFET which will lead to a higher system efficiency and a reducedBOM Board is developed with the primarily goal of providing easyaccess to the different devices for easing the testing phase and formeasuring.

2 A form factor optimization has never been a target for VoltageThe output voltage provided by the 3 phase PFC is here fixed to700 V (Accuracy 5%) and thanks to the SiC technology, the thermalcapability can be extended to higher ranges. The max deliverablepower is 11 kW considering an input voltage of 230 Vac at 50 High fs Range (60 140 kHz) High Efficiency ( @ fs 100 kHz) Wide Input Range (167 to 265 VPH rms) Bi Directional 3 Phase Full Bridge RectifierFigure 2. Topology High LevelVOLTAGE SOURCE INVERTERVDCSAHSALSBHSBLSCHSCLF igure 1. Board PhotoAND9957 3. 3 Phase PFC Block DiagramVOLTAGE SOURCE INVERTER24 V24 VPowerGridEarthEMIF ilterMC UDIGIT ALOpAm VCurrentSensorOpAm VDC B USOpAm psIsolated GateDriverIsolated GateDriverIsolated GateDriverIsolated GateDriverIsolated GateDriverPWM, EN, FAUL T(from & to MCU)Dr iving HSIsolated GateDCDCR elay, FANDCDCGate Dr iverDC BUS2415 DCDCOpAmp5 DCDCDig, VDCDCA nalog DSPMC UANMC UANMC UANGate Dr iverFault Mngm(Logic)CAN InterfaceTo V5 VAPPLICATION/CONTROL OVERVIEWO verall concept can be seen in Figure 3.

3 Since testabilitywas set as the highest priority during concept definition, theboard presented does not aim for highest power densitiesand/or Board behavior is simple, when a 3 phase voltage at50 Hz is provided to the input connector; the output buscapacitor voltage will rise because of nature of the PFCtopology. A bridge less PFC with MOSFET guaranteesa current path from input to output because of the parasiticfreewheeling diode present on each MOSFET. When theMOSFET are all off, the Board simplifies in a 3 phase diodebridge. The rectified input AC voltage will set to a definedlevel depending on the supply voltage amplitude and on theforward voltage of the MOSFET body diodes, however it isexpected that at least 167 Vrms are given at the input.

4 Forthis reason, a resistor on two different lines serves as inrushcurrent limiter. Once the bus voltage reaches 400 V, the2 switch flyback converter starts to operate. It provides24 V from which a series of DC/DC regulators generate theother needed voltage levels for powering up the digital andanalog the micro awakes, besides verifying the offsetvoltages for the ADC channels, it starts also monitoring thebus voltage and sensing the input voltages from whichdetermines the frequency and the angle of the phasevoltages. Such angle will be the reference angle of thesystem to achieve the power factor the DC bus voltage becomes flat, the MCU issuesa command to the relay to bypass the resistor and allowa further boost in the output bus voltage.

5 However, thevoltage increment is going to be something lower therectified input voltage amplitude, 6 VPH, will wait until the bus voltage becomes flat again inorder to start controlling the bus voltage to the targeted valueof 700 V. Target value does not change in a single step buta smooth ramp generator will bring the bus value accordinga parametrized slope to the final 700 PFC implements only one hardware protection,against overcurrent events leveraging the DESAT functionality of the NCV51705 gate driver. A thresholdvalue of 50 A is set on the Board given the characteristic ofthe NVHL080N120SC1 Silicon Carbide MOSFET(N Channel, 1200 V, 80 mW, TO247 3L).

6 AND9957 the fault lines are collected together to generatea single input to the MCU which provides a hardware stopto the PWM generation. A reset of the failure conditions ispossible only by a reset command sent through a GUI or bya power down/power up sequence, basically it representsa HW/SW reset. The Figure 4 summarizes the high levelSW 4. Flow Diagram of Preliminary Steps before Activating DC Bus Voltage RegulationCONTROL HANDLER(FLOW DIAGRAM BEFORE STARTING THE OUT VOLTAGE CONTROL ALGORITHM)IDLE(Ini aliza on)ADC OFFSETVERIFICATIONINRUSH RELAYAdc offsetvalidatedvBus1 notstableINRUSH OVERvBus2 notstableDC BUSVOLTAGE_CONTROL(normal behavior)vBus2 stableFAULT HANDLER(DESAT FAILURE FEEDBACK MANAGEMENT)NO_FAULTFAULTTEMPORARYFAULTPE RMANENTRESET FAULTTMR_EXPIRED && fault_cnt < NUMBEROF THR.

7 FAULTERRORSTOPWait 5 the application is sitting in the DC BUS voltagecontrol state and in case of no failure events, the MCU willrun the field oriented (FOC) voltage control control algorithm is similar to a motor control onewhere the inner loops control the current components. Outerloop controls the bus voltage. Since the goal of the PFC is toguarantee 0 of phase delay between each phase voltage andphase current, the voltage regulation acts on the D axescurrent. Q axes current is set to be 0. D axes represents the ACTIVE power branch, while Q axes represents the REACTIVE power branch. Figure 5 shows the blockdiagram of the control 5. Control Block DiagramVOLTAGEREGULATIONVBUS,REFVBUS,MEA SCURRENTREGULATIONID,REFVA,REFIQ,REF= 0IQ,MEASMODULATIONFOR DUTY CYCLEGENERATIONVB,REFVC,REFdA,REFdB,REFd C,REFVBUS,MEASANALOGSENSINGVBUS, VPHASES, IPHASESID,MEAS VOLTID,MEASIQ,MEASVBUS,MEAS VOLTThe analog quantities sampled to perform the controlalgorithm are: Phase currents (x3); Line voltages, since the neutral point is not provided at theinput connector (x3); DC bus line to line voltages are used to determine the actualposition of the AC voltage phasor.

8 The angle, theta, is thenused for regulated the current phase delay to 0 that is themain target of the PFC. The voltage position is used forswitching from stationary ABC system reference into therotating DQ frame by means of Clark and Parketransformation (for the PFC, D axes means the amplitude ofthe phase voltage phasor).By knowing theta, all the electrical quantities can be thenexpressed in the DQ system, such simplification will ensurethe usage of simple PI/PID regulators. Just as a side note,PID stands for Proportional Integral and Derivativeregulation that may be applied singularly or a combinationof them to the system. In any case, the proper selectiondepends on the transfer function of the plant to be regulators indeed can effectively regulates an error tozero when a constant is provided as reference quantity, whileare not capable of regulating AC reference quantities.

9 In anycase, a calibration of PI regulators are needed in order toensure proper system stability with a good trade offbetween PI loop bandwidth and time response. It is typicalto expect fast response for the current loop (internal) andlower response on the external loop (voltage).In the Figure 7, a more detailed picture of theimplemented control loop is provided. Such control loop isrunning at 20kHz no matter what is going to be the selectedPWM modulation frequency. PWM frequency is almostindependent from the control frequency although there isa synchronization procedure in place in order to have ADCperipheral triggered by a specific PWM counter procedure allows to keep a good relationship amongphase currents, in a star connected three phase system withisolated neutral it is expected to have the instantaneous valueof the sum of the current equal to MCU selected is a general purpose one, based on anArm M3, clock frequency 84 MHz, single S/H and ADCwith multiplexed input channels, 1 MSPS, and 12 time for one ADC conversion is around of the reading delay, of the fast PWM frequency.

10 Of the instantaneous switches status and of the boostinductance, the current flowing in each phase can changequite significantly in very short time. Therefore, in order toovercome such problematic situation, the currents aresampled across three continuous PWM periods. This meansthat the minimum PWM frequency selectable for a properfunctionality is three times the control strategy, thus of course are also present on the max PWMfrequency allowed, and it is 140 kHz. This limitation isintroduced by the wait time needed to perform themeasurement in each PWM period before triggering againthe ADC peripheral for a new measurement. Figure 6displays the reason behind this 6.