NCP51200 - Linear Voltage Regulator 3 A for DDR1, DDR2, …

1 Semiconductor Components Industries, LLC, 2016 June, 2021 Rev. 141 Publication Order Number: NCP51200 /DLinear Voltage Regulator3 A for DDR1, DDR2, DDR3,LPDDR3, DDR4 VTTT erminationNCP51200, NCV51200 The NCP/NCV51200 is a source/sink Double Data Rate (DDR)termination Regulator specifically designed for low input Voltage andlow noise systems where space is a key NCP/NCV51200 maintains a fast transient response and onlyrequires a minimum output capacitance of 20 mF. The NCP/NCV51200supports a remote sensing function and all power requirements forDDR VTT bus termination. The NCP/NCV51200 can also be used inlow power chipsets and graphics processor cores that requiredynamically adjustable output NCP/NCV51200 is available in the thermally efficient DFN10 Exposed Pad wettable flank package, and is rated both Green andPb For Automotive Applications Input Voltage Rails: Supports V, V and 5 V Rails PVCC Voltage Range: to V Integrated Power MOSFETs Fast Load Transient Response PGOOD Logic output pin to Monitor VTT Regulation EN Logic input pin for Shutdown mode VRI Reference Input Allows for Flexible Input Tracking EitherDirectly or Through Resistor Divider Remote Sensing (VTTS) Built in Soft Start, Under Voltage Lockout and Over Current Limit Thermal Shutdown Small, Low Profile 10 pin, 3x3 DFN Package NCV51200 MWTXG (SFS), NCV51200 MLTXG (SLP).

2 WettableFlank Options for Enhanced Optical Inspection NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC Q100 Qualified and PPAP Capable* These Devices are Pb Free and are RoHS CompliantApplications DDR Memory Termination Desktop PC s, Notebooks, and Workstations Servers and Networking equipment Telecom/Datacom, GSM Base Station Graphics Processor Core Supplies Set Top Boxes, LCD TV/PDP TV, Copier/Printers Chipset/RAM Supplies as Low as V Active Bus 485 CPIN CONNECTIONMARKING DIAGRAMSXX= Specific Device CodeA= Assembly LocationL= Wafer Lot (Optional character )Y= YearW= Work WeekG= Pb Free Package51200 XXALYWGG(Note: Microdot may be in either location)12345109876 VCCPGOODGNDENVROVRIPVCCVTTPGNDVTTSGND+Ex posed PadDFNW10 CASE 507 AMSee detailed ordering, marking and shipping information in thepackage dimensions section on page 8 of this data INFORMATIONNCP51200, FUNCTION DESCRIPTIONPin NumberPin NamePin Function1 VRIVTT External Reference Input ( set to VDDQ / 2 thru resistor network ).

3 2 PVCCP ower input. Internally connected to the output source Output of the Linear Ground. Internally connected to the output sink Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to theremote DDR termination bypass Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND ceramic Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connectto VDDQ for normal Good (Open Drain output).10 VCCA nalog power supply input. Connect to GND thru a 1 mF ceramic for thermal connection. The exposed pad must be connected to the ground plane using multiplevias for maximum power dissipation MAXIMUM RATINGSR atingSymbolValueUnitVCC, PVCC, VTT, VTTS, VRI, VRO (Note 1) to , PGOOD (Note 1) to to GND (Note 1) to + TemperatureTSTG 55 to 150 COperating Junction Temperature RangeTJ150 CESD Capability, Human Body Model (Note 2)ESDHBM2000 VStresses exceeding those listed in the Maximum Ratings table may damage the device.

4 If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating This device series incorporates ESD protection and is tested by the following method:ESD Human Body Model tested per AEC Q100 002 (EIA/JESD22 A114)ESD Machine Model tested per AEC Q100 003 (EIA/JESD22 A115)Latchup Current Maximum Rating tested per JEDEC standard: RATINGSP ackageTA = 255C Power RatingDerating Factor above TA = 255 CTA = +855C Power Rating10 Pin W19 mW/ WTHERMAL INFORMATIONS ymbolThermal MetricNCP51200 (*)DFN 3x3mm10 pinsUnitRqJAJunction to ambient thermal C/WRqJC(top)Junction to case (top) thermal C/WRqJBJunction to board thermal resistance (1mm from package) C/WYJTJ unction to top thermal C/WYJBJ unction to board thermal resistance (1mm from package) C/WRqJC(bot)Junction to case (bot) thermal C/W*1S2P JEDEC JESD51 7 PCB with 240 sqmm, 2 oz copper heat , OPERATING CONDITIONSR atingSymbolValueUnitSupply to RangeVRO to to , VTT, VTTS, EN, PGOOD to to + Free Air TemperatureTA 40 to +125 CFunctional operation above the stresses listed in the Recommended Operating Ranges is not implied.

5 Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device CHARACTERISTICS 40 C TA 125 C; VCC = V; PVCC = V; VRI = VTTS = V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise CurrentVCC Supply CurrentTA = +25 C, EN = V, No Shutdown CurrentTA = +25 C, EN = 0 V, VRI = 0 V, No LoadIVCC SHD6580mATA = +25 C, EN = 0 V, VRI > V, No Load200400 VCC UVLO ThresholdWake up, TA = +25 Supply CurrentTA = +25 C, EN = V, No LoadIPVCC150mAPVCC Shutdown CurrentTA = +25 C, EN = 0 V, No LoadIPVCC OutputVTT Output Offset VoltageVRO = V (DDR1), ITT = 0 AVOS 15+15mVVRO = V (DDR2), ITT = 0 A 15+15 AMN suffix, VRO = V (DDR4), ITT = 0 A 15+15 PVCC = V, VRO = V (DDR3), ITT = 0 A 15+15 VTT Voltage Tolerance to VRO 2 A ITT +2 A 25+25mVSource Current LimitVTTS = 90% * Current LimitVTTS = 110% * start Current LimitTimeoutTSS200msDischarge MOSFETOn resistanceVRI = 0 V, VTT = V, EN = 0 V, TA = +25 CRDIS1825 WVRI Input ReferenceVRI Voltage Input bias CurrentEN = VIRI+1mAVRI UVLO VoltageVRI risingVRI UVLO360390435mVHysteresisVRI HYS60 VRO Output ReferenceVRO VoltageVRIVVRO Voltage Tolerance to VRIIRO = 10 mA, V VRI V 15+15mVAMN suffix, IRO = 1 mA, VRI = V 12+12 VRO Source Current LimitVRO = 0 V1040mAVRO Sink Current LimitVRO = 0 V1040mANCP51200, CHARACTERISTICS 40 C TA 125 C; VCC = V; PVCC = V; VRI = VTTS = V; EN = VCC; COUT = 3 x 10 mF (Ceramic).

6 Unless otherwise Powergood ComparatorPGOOD Lower Threshold(with respect to VRO) 20% Upper Threshold(with respect to VRO) Hysteresis5%PGOOD Start up DelayStart up rising edge, VTTS within 15% ofVRO2msPGOOD Leakage CurrentVTTS = VRI (PGOOD = True)PGOOD = VCC + V1mAPGOOD = False DelayVTTS is beyond 20% PGOOD trip thresholds10msPGOOD Output Low VoltageIGOOD = 4 , CHARACTERISTICS 40 C TA 125 C; VCC = V; PVCC = V; VRI = VTTS = V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise Enable LogicLogic Input ThresholdEN Logic Logic VoltageEN Leakage CurrentEN pin, TA = +25 CIILEAK 1+1mAThermal ShutdownThermal ShutdownTemperatureTSD150 CThermal Shutdown HysteresisTSH25 CProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different 1.

7 Typical DDR 3 Application SchematicNCP51200, 2. Block DiagramNCP51200, NCP51200 is a sink/source tracking terminationregulator specifically designed for low input Voltage andlow external component count systems where space is a keyapplication parameter. The NCP51200 integrates ahigh performance, low dropout (LDO) Linear regulatorthat is capable of both sourcing and sinking current. TheLDO Regulator employs a fast feedback loop so that smallceramic capacitors can be used to support the fast loadtransient response. To achieve tight regulation withminimum effect of trace resistance, a remote sensingterminal, VTTS, should be connected to the positive terminalof the output capacitors as a separate trace from the highcurrent path from Generation of Internal Voltage ReferenceThe output Voltage , VTT, is regulated to VRO.

8 When VRIis configured for standard DDR termination applications,VRI can be set by an external equivalent ratio Voltage dividerconnected to the memory supply bus (VDDQ). TheNCP51200 supports VRI Voltage from V to V,making it versatile and ideal for many types of low powerLDO Reference OutputWhen it is configured for DDR termination applications,VRO generates the DDR VTT reference Voltage for thememory application. It is capable of supporting both asourcing and sinking load of 10 mA. VRO becomes activewhen VRI Voltage rises to 435 mV and VCC is above theUVLO threshold. When VRO is less than 360 mV, it isdisabled and subsequently discharges to GND through aninternal 10 kW MOSFET. VRO is independent of the EN StartThe soft start function of the VTT pin is achieved via acurrent clamp.

9 The current clamp allows the outputcapacitors to be charged with low and constant current,providing a Linear ramp up of the output Voltage . WhenVTT is outside of the power good window, the currentclamp level is one half of the full over current limit (OCL)level. When VTT rises or falls within the PGOOD window, thecurrent clamp level switches to the full OCL soft start function is completely symmetrical; itworks not only from GND to the VRO Voltage but also fromPVCC to the VRO Enable ControlWhen EN is driven high, the NCP51200 VTT regulatorbegins normal operation. When EN is driven low, VTT isdischarges to GND through an internal 18 W remains on when EN is driven PowerGoodThe NCP51200 provides an open drain PGOOD outputthat goes high when the VTT output is within 20% of de asserts within 10 ms after the output exceeds thelimits of the PowerGood window.

10 During initial VTTstartup, PGOOD asserts high 2 ms after the VTT enters powergood window. Because PGOOD is an open drain output, a100 kW, pull up resistor between PGOOD and a stable activesupply Voltage rail is LDO has a constant over current limit (OCL). Notethat the OCL level reduces by one half when the outputvoltage is not within the power good window. This reductionis non latch protection. For VCC under Voltage lockout(UVLO) protection, the NCP51200 monitors VCC the VCC Voltage is lower than the UVLO thresholdvoltage, both the VTT and VRO regulators are powered shutdown is also non latch Shutdown with HysteresisIf the NCP51200 is to operate in elevated temperatures forlong durations, care should be taken to ensure that themaximum operating junction temperature is not guarantee safe operation, the NCP51200 provideson chip thermal shutdown protection.