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PCF8563 Real-time clock/calendar - NXP

1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) 4N 0[2] unused 3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic 0 for normal operation Section 8.11.1 1[1] Power-On Reset (POR) override may be enabled 2to0 N 000[2] unused

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