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Semiconductor Packaging Assembly Technology - …

Semiconductor Packaging Assembly TechnologyIntroductionThis chapter describes the fundamentals of the processesused by National Semiconductor to assemble IC devices inelectronic packages. Electronic Packaging provides the in-terconnection from the IC to the printed circuit board (PCB).Another function is to provide the desired mechanical andenvironmental protection to ensure reliability and perfor-mance. Three fundamental Assembly flow processes (Table1) are covered in this chapter: 1) plastic leadframe-basedpackages, 2) plastic ball grid array (PBGA), and 3) 1. Assembly Flow Processes for ElectronicPackagesPlastic(Leadframe)Plas tic (BGA)HermeticWafer SortWafer SortWafer Sort2nd Optical2nd Optical2ndOpticalWafer MountWafer MountWaferMountWafer SawingWafer SawingWaferSawingDie AttachDie AttachDie AttachWire BondWire BondWire Bond3rd Optical3rd Optical3rdOpticalEncapsulate(Mold Compound)Encapsulate (MoldCompound or GlobTop)Lid SealDejunkBall Attach andReflowLeakageTestDeflashSingulateMark ingBall InspectionPlatingMarkingTrim and FormFinal InspectionThe fundamental package Assembly pr

Semiconductor Packaging Assembly Technology Introduction This chapter describes the fundamentals of the processes used by National Semiconductor to assemble IC …

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Transcription of Semiconductor Packaging Assembly Technology - …

1 Semiconductor Packaging Assembly TechnologyIntroductionThis chapter describes the fundamentals of the processesused by National Semiconductor to assemble IC devices inelectronic packages. Electronic Packaging provides the in-terconnection from the IC to the printed circuit board (PCB).Another function is to provide the desired mechanical andenvironmental protection to ensure reliability and perfor-mance. Three fundamental Assembly flow processes (Table1) are covered in this chapter: 1) plastic leadframe-basedpackages, 2) plastic ball grid array (PBGA), and 3) 1. Assembly Flow Processes for ElectronicPackagesPlastic(Leadframe)Plas tic (BGA)HermeticWafer SortWafer SortWafer Sort2nd Optical2nd Optical2ndOpticalWafer MountWafer MountWaferMountWafer SawingWafer SawingWaferSawingDie AttachDie AttachDie AttachWire BondWire BondWire Bond3rd Optical3rd Optical3rdOpticalEncapsulate(Mold Compound)Encapsulate (MoldCompound or GlobTop)Lid SealDejunkBall Attach andReflowLeakageTestDeflashSingulateMark ingBall InspectionPlatingMarkingTrim and FormFinal InspectionThe fundamental package Assembly processes for lead-frame and hermetic Packaging have remained relatively un-changed over the past 30 years, though the equipment andmaterials have undergone considerable advancement.

2 As-sembly equipment is no longer as labor intensive. Process-ing is typically carried out on automated equipment designedand manufactured for high-volume production. Materials areof higher purity and have properties tailored for a specific Technology Introduction AndVerificationBefore implementing a new Technology , either a material oran Assembly Technology , National Semiconductor utilizes arigorous system to characterize and verify the suitability ofthe change for high-volume FeasibilityA preliminary analysis of the process or material is con-ducted to determine the feasibility of introducing a newor changing a material/process Technology . This analy-sis includes a benchmark assessment of available andcompeting PrototypesPrototype parts are assembled to provide an initialsample size for AssemblyParts are assembled in production equipment to furtherverify the Technology TestingAssembled devices are put through testing to ensure theintegrity of the Process CharacterizationA full process characterization is conducted to determinethe readiness of the new Technology for high-volumemanufacturing.

3 This step utilizes design of experiment(DOE) Manufacturing VerificationProduction lots are assembled and put through the re-quired qualification test to determine package ProductionAfter successfully completing the previous steps, thetechnology is released for full PreparationDie preparation is common to all three types of wafers are sorted at the Assembly site and stored in adie bank. A 2nd optical visual inspection is conducted to in-spect for defects before the wafers are released for wafers are mounted on a backing tape that adheres tothe back of the wafer. The backing/mounting tape providessupport for handling during wafer saw and the die attach wafer saw process cuts the individual die from the waferleaving the die on the backing tape.

4 The wafer saw equip-ment consists of automated handling equipment, saw blade,and an image recognition system. The image recognitionsystem maps the wafer surface to identify the areas to becut, known as the saw street. DI Water is dispensed on thewafer during the saw process to wash away particles (SiAugust 1999 Semiconductor Packaging Assembly Technology 2000 National Semiconductor Preparation(Continued)Dust) and to provide lubrication during the dicing are dried by spinning the wafer at a high RPM beforegoing to the die attach Leadframe-Based PackagesDIE ATTACHDie attach provides the mechanical support between the sili-con die and the substrate, ,. leadframe, plastic or ceramicsubstrate. The die attach is also critical to the thermal and,for some applications, the electrical performance of the die attach equipment is configured to handle the incom-ing wafer and substrate simultaneously.

5 An image recogni-tion system identifies individual die to be removed from thewafer backing/Mounting tape, while die attach material isdispensed in controled amounts on to the substrate. A nonpierce through plunge up needle/s assists to separate an in-dividual die to be picked by the collet on the pick-up head ofthe die attacher. Finally, the die is aligned in the proper orien-tation and position on the type of material used for die attach is a function of thepackage type and performance 2listsgeneral materials for the various package 2. Overview of Die Attach MaterialsPackage TypeMaterialRequirementsPlastic(Leadfram e)Epoxy (silverfilled) ModifiedEpoxies CyanateEster BlendsLow MoistureAbsorptionThermalDissipationPlas tic (Power)Solder (Softsolders)UniformIntermetallicFormati onThermalDissipationThe epoxy and cyanate ester are two types of polymers usedas a die attach between the die and the leadframe.

6 Depend-ing on the leadframe design, adhesion may be directly tocopper, silver plating, or palladium plating. Die attach mate-rials are filled with silver particles to increase the thermal dis-sipation properties. Material is dispensed from syringes incontrolled amounts. These materials have defined shelvelifes and, therefore, the recommended guidelines must befollowed when handling in a manufacturing environment. Af-ter placement of the die, the die attach is cured; typical curetemperatures are in the 125-175 C rangeSome power packages use soft solders as the die attachmaterial between the die and the leadframe. These materialsare lead-tin based and provide an excellent mechanicalbond with superior thermal dissipation properties comparedto polymer die attach.

7 A wafer back metal is required to formthe bond between the solder and the wafer. An intermetalliclayer forms between two interfaces to provide the mechani-cal strength needed for die attach: 1) between the solder andthe wafer backmetal and 2) the solder and the solder die attach equipment dispenses the solder in wireor ribbon form onto the leadframe. Temperatures used in sol-der die attach range from 260 C to 345 C depending on thesolder metallurgy coverage of the material dispensed during the die attachprocess is critical to the reliability and performance of thepackage. The presence of voids and variations in thicknessare undesirable. Excessive or insufficient coverage of the dieattach material makes the device susceptible to reliabilityfailures.

8 The adhesion strength of the die attach is weakenedby the presence of voids, particularly during temperaturecycle excursions, and can impact the ability of the die attachmaterial to dissipate heat away from the device. Lack ofthickness control can contribute to reliability failures and im-pact the subsequent wire bond process. Typical Bond linethickness is between 1 to 2 BONDWire bonds are the most common means of providing anelectrical connection from the IC device to the substrate/Leadframe. The wire bond process must achieve highthroughputs and production yields to be acceptable on a costbasis. High-speed wire bond equipment consists of a han-dling system to feed the substrate/leadframe into the workarea.

9 Image recognition systems ensure the die is orientatedto match the bonding diagram for a particular device. Wiresare bonded one wire at a bonding is used with gold and copper wire. Thewire is fed through a ceramic capillary. A combination of tem-perature and ultrasonic energy forms the metallic wire each interconnection two wire bonds are formed, one atthe die and the other at the leadframe/substrate. The firstbond involves the formation of a ball with an electric flame-off (EFO) process. The ball is placed in direct contact withinthe bond pad opening on the die, under load (Bond Force)and ultrasonic energy within a few milliseconds (Bond Time)& forms a ball bond at the Al bond pad metal. The BondForce, US Power & Time forms a Au-Al intermetallic layerthat makes the connection on the Bond Pad of the Die.

10 Thewire is then lifted to form a loop and then is placed in contactwith the desired bond area of the leadframe/substrate toform a wedge bond. Bonding temperature, ultrasonic energy,and bond force & Time are key process parameters con-trolled to form a reliable connection from the Die to theLeadframe/Substrate. The Shape of the loop for a specificcapability is controlled by the software that drives the motionof the bondhead. The Ball Bond reliability at 1st bond (ballBond) & 2nd bond (wedge) is very sensitive to any move-ment of the Die or the Substrate/leadframe. So during wirebond operation, the die & the substrate/leadframe must beheld major issue with regards to 1st bond reliability is theBrittle intermetallic (Purple Plague; AuAl2) formation.


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