NUP2202W1 ESD Protection Diode - ON …

1 Semiconductor Components Industries, LLC, 2009 October, 2017 Rev. 41 Publication Order Number: NUP2202W1 /DNUP2202W1 ESD Protection DiodeLow Clamping VoltageThe NUP2202W1 surge Protection is designed to protect high speeddata lines from ESD, EFT, and : Low Clamping Voltage Stand Off Voltage: 5 V Low Leakage Protection for the Following IEC Standards:IEC 61000 4 2 Level 4 ESD Protection UL Flammability Rating of 94 V 0 This is a Pb Free DeviceTypical Applications: High Speed Communication Line Protection USB and Power and Data Line Protection Digital Video Interface (DVI) and HDMI Monitors and Flat Panel Displays MP3 MAXIMUM RATINGS (TJ = 25 C unless otherwise noted)RatingSymbolValueUnitPeak Power Dissipation8 x 20 mS @ TA = 25 C (Note 1)Ppk500 WOperating Junction Temperature RangeTJ 40 to +125 CStorage Temperature RangeTstg 55 to +150 CLead Solder Temperature Maximum (10 Seconds)TL260 CHuman Body Model (HBM)Machine Model (MM)IEC 61000 4 2 Air (ESD)IEC 61000 4 2 Contact (ESD)ESD160004002000020000 VIEC 61000 4 4 (5/50 ns)EFT40 AStresses exceeding those listed in the Maximum Ratings table may damage thedevice.

2 If any of these limits are exceeded, device functionality should not beassumed, damage may occur and reliability may be Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2).See Application Note AND8308/D for further description of survivability 88 LOW CAPACITANCEDIODE SURGE PROTECTIONARRAY 500 WATTS PEAK POWER 6 VOLTSMARKING DIAGRAMD evicePackageShipping ORDERING INFORMATIONSC 88 CASE 419 BPLASTICPIN CONFIGURATIONAND SCHEMATIC6 I/O5 VP4 N/CI/O 1VN 2N/C 88Pb Free3000/Tape & Reel For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011 MGG1662 = Specific Device CodeM = Date CodeG= Pb Free Package(Note: Microdot may be in either location)SCALE 2 CHARACTERISTICS(TA = 25 C unless otherwise noted)SymbolParameterIPPM aximum Reverse Peak Pulse CurrentVCClamping Voltage @ IPPVRWMW orking Peak Reverse VoltageIRMaximum Reverse Leakage Current @ VRWMVBRB reakdown Voltage @ ITITTest CurrentIFForward CurrentVFForward Voltage @ IFPpkPeak Power DissipationCCapacitance @ VR = 0 and f = MHz*See Application Note AND8308/D for detailed explanations ofdatasheet DirectionalIPPIFVIIRITVRWMVCVBRVFELECTRI CAL CHARACTERISTICS (TJ=25 C unless otherwise specified)ParameterSymbolConditionsMinTy pMaxUnitReverse Working VoltageVRWM(Note 2) VoltageVBRIT = 1 mA, (Note 3) Leakage CurrentIRVRWM = 5 VoltageVCIPP = 5 A (Note 4) VoltageVCIPP = 8 A (Note 4)

3 Peak Pulse CurrentIPP8x20 ms Waveform (Note 4)28 AJunction CapacitanceCJVR = 0 V, f = 1 MHz between I/O Pins and CapacitanceCJVR = 0 V, f = 1 MHz between I/O VoltageVCPer IEC 61000 4 2 (Note 6)Figure 1 and 2V2. surge Protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greaterthan the DC or continuous peak operating voltage VBR is measured at pulse test current Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2).5. Surge current waveform per Figure For test procedure see Figures 3 and 4 and Application Note AND8307 1. ESD Clamping Voltage ScreenshotPositive 8 kV Contact per IEC61000 4 2 Figure 2. ESD Clamping Voltage ScreenshotNegative 8 kV Contact per IEC61000 4 61000 4 2 Volt-age (kV)First PeakCurrent(A)Current at30 ns (A)Current at60 ns (A) 4 2 Waveform100%I @ 30 nsI @ 60 nstP = ns to 1 nsFigure 3.

4 IEC61000 4 2 SpecFigure 4. Diagram of ESD Test Setup50 WCableDeviceUnderTestOscilloscopeESD Gun50 WThe following is taken from Application NoteAND8308/D Interpretation of Datasheet Parametersfor ESD Voltage ClampingFor sensitive circuit elements it is important to limit thevoltage that an IC will be exposed to during an ESD eventto as low a voltage as possible. The ESD clamping voltageis the voltage drop across the ESD Protection Diode duringan ESD event per the IEC61000 4 2 waveform. Since theIEC61000 4 2 was written as a pass/fail spec for largersystems such as cell phones or laptop computers it is notclearly defined in the spec how to specify a clamping voltageat the device level. ON Semiconductor has developed a wayto examine the entire voltage waveform across the ESDprotection Diode over the time domain of an ESD pulse in theform of an oscilloscope screenshot, which can be found onthe datasheets for all ESD Protection diodes.

5 For moreinformation on how ON Semiconductor creates thesescreenshots and how to interpret them please refer toAND8307 5. 8 x 20 ms Pulse Waveform1009080706050403020100020406080t , TIME (ms)% OF PEAK PULSE CURRENTtPtrPULSE WIDTH (tP) IS DEFINEDAS THAT POINT WHERE THEPEAK CURRENT DECAY = 8 msPEAK VALUE IRSM @ 8 msHALF VALUE IRSM/2 @ 20 PERFORMANCE CURVES(TJ = 25 C unless otherwise noted)Figure 6. Pulse Derating Curve10090807060504030201000255075100125 150175200TA, AMBIENT TEMPERATURE ( C)Figure 7. Junction Capacitance vs Reverse , REVERSE VOLTAGE (V)JUNCTION CAPACITANCE (pF)2345I/O linesI/O GroundPEAK POWER DISSIPATION (%) 8. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform)20100010 PEAK PULSE CURRENT (A)CLAMPING VOLTAGE (V) INFORMATIONThe NUP2202W1 is a low capacitance surge protectiondiode array designed to protect sensitive electronics such ascommunications systems, computers, and computerperipherals against damage due to ESD events or transientovervoltage conditions.

6 Because of its low capacitance, itcan be used on high speed I/O data lines. The integrateddesign of the NUP2202W1 offers surge rated, lowcapacitance steering diodes and a surge Protection diodeintegrated in a single package (SC 88). If a transientcondition occurs, the steering diodes will drive the transientto the positive rail of the power supply or to ground. Thesurge Protection device protects the power line againstovervoltage conditions to avoid damage to the power supplyand any downstream Device Configuration OptionsThe NUP2202W1 is able to protect two data lines againsttransient overvoltage conditions by driving them to a fixedreference point for clamping purposes. The steering diodeswill be forward biased whenever the voltage on theprotected line exceeds the reference voltage (Vf or VCC +Vf).

7 The diodes will force the transient current to bypass thesensitive lines are connected at pins 1 and 6. The negativereference is connected at pin 2. This pin must be connecteddirectly to ground by using a ground plane to minimize thePCB s ground inductance. It is very important to reduce thePCB trace lengths as much as possible to minimize 1 Protection of two data lines and the power supply usingVCC as 1I/O 2 VCCFor this configuration, connect pin 5 directly to thepositive supply rail (VCC), the data lines are referenced tothe supply voltage. The internal surge Protection diodeprevents overvoltage on the supply rail. Biasing of thesteering diodes reduces their 2 Protection of two data lines with bias and power supplyisolation kI/O 1I/O 2654123 The NUP2202W1 can be isolated from the power supplyby connecting a series resistor between pin 5 and VCC.

8 A10 kW resistor is recommended for this application. Thiswill maintain bias on the internal surge Protection andsteering diodes, reducing their 3 Protection of two data lines using the internal surgeprotection Diode as 1I/O 2NC654123In applications lacking a positive supply reference orthose cases in which a fully isolated power supply isrequired, the internal surge Protection can be used as thereference. For these applications, pin 5 is not connected. Inthis configuration, the steering diodes will conductwhenever the voltage on the protected line exceeds theworking voltage of the surge Protection plus one Diode drop(Vc = Vf + VRWM).ESD Protection of Power Supply LinesWhen using diodes for data line Protection , referencing toa supply rail provides advantages.

9 Biasing the diodesreduces their capacitance and minimizes signal this topology with discrete devices does havedisadvantages. This configuration is shown LineIESDposIESDnegVF + VCC VFIESDposIESDnegPowerSupplyProtectedDevi ceLooking at the figure above, it can be seen that when apositive ESD condition occurs, Diode D1 will be forwardbiased while Diode D2 will be forward biased when anegative ESD condition occurs. For slower transientconditions, this system may be approximated as follows:For positive pulse conditions:Vc = VCC + VfD1 For negative pulse conditions:Vc = VfD2 ESD events can have rise times on the order of somenumber of nanoseconds. Under these conditions, the effectof parasitic inductance must be considered. A pictorialrepresentation of this is shown LineIESDposIESDnegVC = VCC + Vf + (L diESD/dt)IESDposIESDnegPowerSupplyProtec tedDeviceVC = Vf (L diESD/dt)An approximation of the clamping voltage for these fasttransients would be:For positive pulse conditions:Vc = VCC + Vf + (L diESD/dt)For negative pulse conditions:Vc = Vf (L diESD/dt)As shown in the formulas, the clamping voltage (Vc) notonly depends on the Vf of the steering diodes but also on theL diESD/dt factor.

10 A relatively small trace inductance canresult in hundreds of volts appearing on the supply rail. Thisendangers both the power supply and anything attached tothat rail. This highlights the importance of good boardlayout. Taking care to minimize the effects of parasiticinductance will provide significant benefits in with good board layout, some disadvantages are stillpresent when discrete diodes are used to suppress ESDevents across datalines and the supply rail. Discrete diodeswith good transient power capability will have larger die andtherefore higher capacitance. This capacitance becomesproblematic as transmission frequencies increase. Reducingcapacitance generally requires reducing die size. Thesesmall die will have higher forward voltage characteristics attypical ESD transient current levels.