MC74VHC1GT32 - 2-Input OR Gate/CMOS Logic Level Shifter

1 Semiconductor Components Industries, LLC, 2013 May, 2018 Rev. 131 Publication Order Number:MC74 VHC1GT32/DMC74 VHC1GT322- input OR gate /CMOSL ogic Level ShifterThe MC74 VHC1GT32 is an advanced high speed cmos 2 inputOR gate fabricated with silicon gate cmos technology. It achieveshigh speed operation similar to equivalent Bipolar Schottky TTLwhile maintaining cmos low power internal circuit is composed of three stages, including a bufferoutput which provides high noise immunity and stable device input is compatible with TTL type input thresholds andthe output has a full 5 V cmos Level output swing. The input protectioncircuitry on this device allows overvoltage tolerance on the input ,allowing the device to be used as a Logic Level translator from 3 VCMOS Logic to 5 V cmos Logic or from V cmos Logic to 3 VCMOS Logic while operating at the high voltage power MC74 VHC1GT32 input structure provides protection whenvoltages up to 7 V are applied, regardless of the supply voltage.

2 Thisallows the MC74 VHC1GT32 to be used to interface 5 V circuits to3 V circuits. The output structures also provide protection whenVCC = 0 V. These input and output structures help prevent devicedestruction caused by supply voltage input /output voltage mismatch,battery backup, hot insertion, High Speed: tPD = ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25 C TTL Compatible Inputs: VIL = V; VIH = 2 V cmos Compatible Outputs: VOH > VCC; VOL < VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 65; Equivalent Gates = 15 NLV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC Q100 Qualified and PPAP Capable These Devices are Pb Free and are RoHS CompliantFigure 1.

3 Pinout (Top View)VCCIN BIN AOUT YGNDIN AIN BOUT Y 1 Figure 2. Logic 88A / SC70 5 / SOT 353DF SUFFIXCASE 419 ATSOP 5 / SOT23 5 / SC59 5DT SUFFIXCASE 4831155 PIN ASSIGNMENT123 GNDIN BIN A45 VCCOUT YLLHHLHLHFUNCTION TABLEI nputsOutputABLHHHYSee detailed ordering and shipping information in the packagedimensions section on page 4 of this data INFORMATION15VN M GGVN= Device CodeM= Date Code*G= Pb Free Package15VN MGGM*Date Code orientation and/or position may varydepending upon manufacturing location.(Note: Microdot may be in either location) RATINGSS ymbolCharacteristicsValueUnitVCCDC Supply Voltage to + input Voltage to + Output VoltageVCC = 0 High or Low State to to VCC + Diode Current 20mAIOKO utput Diode CurrentVOUT < GND; VOUT > VCC+20mAIOUTDC Output Current, per Pin+25mAICCDC Supply Current, VCC and GND+50mAPDP ower dissipation in still airSC 88A, TSOP 5200mWqJAThermal resistanceSC 88A, TSOP 5333 C/WTLLead temperature, 1 mm from case for 10 s260 CTJJ unction temperature under bias+150 CTstgStorage temperature 65 to +150 CVESDESD Withstand VoltageHuman Body Model (Note 1)Machine Model (Note 2)Charged Device Model (Note 3)> 2000> 200N/AVIL atchupLatchup PerformanceAbove VCC and Below GND at 125 C (Note 4) 500mAStresses exceeding those listed in the Maximum Ratings table may damage the device.

4 If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be Tested to EIA/JESD22 A114 A2. Tested to EIA/JESD22 A115 A3. Tested to JESD22 C101 A4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONSS ymbolCharacteristicsMinMaxUnitVCCDC Supply input Output VoltageVCC = 0 High or Low Temperature Range 55+125 Ctr , tfInput Rise and Fall TimeVCC = V VVCC = V V0010020ns/VDevice Junction Temperature versusTime to Bond FailuresJunctionTemperature CTime, HoursTime, Years801,032, , , , , , , , YEARSNORMALIZED FAILURE RATETJ= 80C TJ= 90C TJ= 100 C TJ= 110 C TJ= 130 C TJ= 120 C FAILURE RATE OF PLASTIC = CERAMICUNTIL INTERMETALLICS OCCURF igure 3. Failure Rate vs. Time Junction ELECTRICAL CHARACTERISTICSVCCTA = 25 CTA 85 C 55 TA 125 CSymbolParameterTest Conditions(V)MinTypMaxMinMaxMinMaxUnitVI HM inimum High LevelInput Low LevelInput High LevelOutput VoltageVIN = VIH or VILVIN = VIH or VILIOH = 50 = VIH or VILIOH = 4 mAIOH = 8 Low LevelOutput VoltageVIN = VIH or VILVIN = VIH or VILIOL = 50 = VIH or VILIOL = 4 mAIOL = 8 InputLeakage CurrentVIN = V or GND0 QuiescentSupply CurrentVIN = VCC or SupplyCurrentInput.

5 VIN = LeakageCurrentVOUT = AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, input tr = tf = ) Symbol Parameter Test Conditions TA = 25 C TA 85 C 55 TA 125 C Unit Min Typ Max Min Max Min Max tPLH,tPHL MaximumPropagation Delay, input A or B to Y VCC = VCL = 15 pFCL = 50 pF ns VCC = VCL = 15 pFCL = 50 pF CIN Maximum InputCapacitance 10 10 10 pFCPDP ower Dissipation Capacitance (Note 5)

6 Typical @ 25 C, VCC = VpF115. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no load dynamicpower consumption; PD = CPD VCC2 fin + ICC *Includes all probe and jig capacitanceCL*TEST POINTDEVICEUNDERTESTOUTPUTF igure 4. Switching WaveformsFigure 5. Test CircuitGND50%50% VCCI nput A or BOutput YtPHLtPLH50% VCCVOLVOHORDERING INFORMATIOND evicePackageShipping M74 VHC1GT32 DFT1 GSC 88A / SOT 353 / SC 70 5(Pb Free)3000 / Tape & ReelNLVVHC1GT32 DFT1G*M74 VHC1GT32 DFT2 GNLVVHC1GT32 DFT2G*M74 VHC1GT32 DTT1 GTSOP 5 / SOT 23 / SC 59(Pb Free)3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

7 *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q100 Qualified and DIMENSIONSNOTES:1. DIMENSIONING AND TOLERANCINGPER ANSI , CONTROLLING DIMENSION: 419A 01 OBSOLETE. NEW STANDARD419A DIMENSIONS A AND B DO NOT INCLUDEMOLD FLASH, PROTRUSIONS, OR ( )MM12 345 AGSD 5 PLHCNJK B SC 88A (SC 70 5/SOT 353)CASE 419A 02 ISSUE L mminches SCALE 20 DIMENSIONSTSOP 5 CASE 483 ISSUE mminches SCALE 10 *For additional information on our Pb Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, FOOTPRINT*NOTES:1. DIMENSIONING AND TOLERANCING PER , CONTROLLING DIMENSION: MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISHTHICKNESS. MINIMUM LEAD THICKNESS IS THEMINIMUM THICKNESS OF BASE DIMENSIONS A AND B DO NOT INCLUDE MOLDFLASH, PROTRUSIONS, OR gate BURRS.

8 MOLDFLASH, PROTRUSIONS, OR gate BURRS SHALL NOTEXCEED PER SIDE. DIMENSION OPTIONAL CONSTRUCTION: AN ADDITIONALTRIMMED LEAD IS ALLOWED IN THIS LEAD NOT TO EXTEND MORE THAN 10 ZDETAIL ZTOP VIEWSIDE VIEWABEND Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patentcoverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards.

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