8-Bit Multiplying Digital-to-Analog Converters (Rev. D)

1 SLAS061D SEPTEMBER 1986 REVISED JUNE 20071 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 DEasily Interfaced to MicroprocessorsDOn-Chip Data LatchesDMonotonic Over the Entire A/D ConversionRangeDSegmented High-Order Bits EnsureLow-Glitch OutputDInterchangeable With Analog DevicesAD7524, PMI PM-7524, and Micro PowerSystems MP7524 DFast Control Signaling for DigitalSignal-Processor Applications IncludingInterface With TMS320 DCMOS Technology KEY PERFORMANCE SPECIFICATIONSR esolutionLinearity errorPower dissipation at VDD = 5 VSetting timePropagation delay time8 Bits1/2 LSB Max5mW Max100ns Max80ns MaxdescriptionThe TLC7524C, TLC7524E, and TLC7524I areCMOS, 8-Bit , Digital-to-Analog Converters (DACs)designed for easy interface to most devices are 8-Bit , Multiplying DACs with input latches and load cycles similar to the write cycles of a randomaccess memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,which produce the highest glitch impulse.

2 The devices provide accuracy to 1/2 LSB without the need for thin-filmresistors or laser trimming, while dissipating less than 5mW operation from a 5V to 15V single supply, these devices interface easily to most microprocessor busesor output ports. The 2- or 4-quadrant Multiplying makes these devices an ideal choice for manymicroprocessor-controlled gain-setting and signal-control TLC7524C is characterized for operation from 0 C to 70 C. The TLC7524I is characterized for operationfrom 25 C to +85 C. The TLC7524E is characterized for operation from 40 C to +85 1998 2007, Texas Instruments Incorporated !" # $% & " !# '%() $!" *!"&+ *%$"# $ " #'&$ $!" # '& ",& "& # &-!# #" % & "##"! *! * .! ! "/+ *%$" ' $&## 0 * &# " &$&##! )/ $)%*&"&#" 0 !)) '! ! &"& #+Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data trademarks are the property of their respective 5678161514131211109 OUT1 OUT2 GNDDB7DB6DB5DB4DB3 RFBREFVDDWRCSDB0DB1DB2321201991011121345 6781817161514 VDDWRNCCSDB0 GNDDB7 NCDB6DB5FN PACKAGE(TOP VIEW)OUT2 OUT1 NCDB2DB1 REFDB4DB3 NCNC No internal connectionRFBD, N, OR PW PACKAGE(TOP VIEW) SLAS061D SEPTEMBER 1986 REVISED JUNE 20072 POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramData InputsData Latches13WR12 CSREF1511DB0(LSB)6DB55DB64DB7(MSB)GND3 OUT22 OUT11 RFB16 RRRR2R2RS-82RS-32RS-2S-12 RTerminal numbers shown are for the D or N maximum ratings over operating free-air temperature range (unless otherwise noted)

3 Supply voltage range, VDD to .. Digital input voltage range, VI to VDD + .. Reference voltage, Vref 25V.. Peak digital input current, II 10 A.. Operating free-air temperature range, TA: TLC7524C 0 C to +70 C.. TLC7524I 25 C to +85 C.. TLC7524E 40 C to +85 C.. Storage temperature range, Tstg 65 C to +150 C.. Case temperature for 10 seconds, TC: FN package +260 C.. Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package +260 C.. package/ordering informationFor the most current package and ordering information, see the Package Option Addendum at the end of thisdocument, or see the TI website at SLAS061D SEPTEMBER 1986 REVISED JUNE 20073 POST OFFICE BOX 655303 DALLAS, TEXAS 75265recommended operating conditionsVDD = 5 VVDD = 15 VUNITMINNOMMAXMINNOMMAXUNITS upply voltage, voltage, Vref 10 10 VHigh-level input voltage, input voltage, setup time, tsu(CS)4040nsCS hold time, th(CS)00nsData bus input setup time, tsu(D)2525nsData bus input hold time, th(D)1010nsPulse duration, WR low, tw(WR)4040nsTLC7524C0+700+70 Operating free-air temperature, TATLC7524I 25+85 25+85 COperating free-air temperature, TATLC7524E 40+85 40+85 Celectrical characteristics over recommended operating free-air temperature range, Vref = 10V,OUT1 and OUT2 at GND (unless otherwise noted)

4 PARAMETERTEST CONDITIONSVDD = 5 VVDD = 15 VUNITPARAMETERTEST CONDITIONSMINTYPMAXMINTYPMAXUNITIIHHigh- level input currentVI = VDD1010 AIILLow-level input currentVI = 0 10 10 AIIkgOutput leakageOUT1DB0 DB7 at 0V,Vref = 10 VWR, CS at 0V, 400 200nAIIkgOutput leakagecurrentOUT2DB0 DB7 at VDD,Vref = 10 VWR, CS at 0V, 400 200nAIDDS upply currentQuiescentDB0 DB7 at VIHmin or VILmax12mAIDDS upply currentStandbyDB0 DB7 at 0V or VDD500500 AkSVSS upply voltage sensitivity, gain/ VDD VDD = 10% capacitance,DB0 DB7, WR, CSVI = 055pFOUT1DB0 DB7 at 0V,WR, CS at 0V3030 CoOutput capacitanceOUT2DB0 DB7 at 0V,WR, CS at 0V120120pFCoOutput capacitanceOUT1DB0 DB7 at VDD,WR, CS at 0V120120pFOUT2DB0 DB7 at VDD,WR, CS at 0V3030 Reference input impedance (REF to GND)520520k SLAS061D SEPTEMBER 1986 REVISED JUNE 20074 POST OFFICE BOX 655303 DALLAS, TEXAS 75265operating characteristics over recommended operating free-air temperature range, Vref = 10V,OUT1 and OUT2 at GND (unless otherwise noted)PARAMETERTEST CONDITIONSVDD = 5 VVDD = 15 VUNITPARAMETERTEST CONDITIONSMINTYPMAXMINTYPMAXUNITL inearity error errorSee Note 1 time (to 1/2 LSB)See Note 2100100nsPropagation delay from digital inputto 90% of final analog output currentSee Note 28080nsFeedthrough at OUT1 or OUT2 Vref = 10V (100kHz sinewave) WR and CS at 0V, DB0 DB7 at coefficient of gainTA = +25 C to MAX CNOTES: 1.

5 Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref OUT1 load = 100 , Cext = 13pF, WR at 0V, CS at 0V, DB0 DB7 at 0V to VDD or VDD to sequenceDB0 DB7 WRCSth(D) tsu(D)tw(WR)th(CS)tsu(CS) SLAS061D SEPTEMBER 1986 REVISED JUNE 20075 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION voltage-mode operationIt is possible to operate the current- Multiplying DAC in these devices in a voltage mode. In the voltage mode,a fixed voltage is placed on the current output terminal. The analog output voltage is then available at thereference voltage terminal. Figure 1 is an example of a current- Multiplying DAC, which is operated in (Analog Output Voltage)OUT2 OUT1 (Fixed Input Voltage)RRR2R2R2R2 RFigure 1. Voltage Mode OperationThe relationship between the fixed-input voltage and the analog-output voltage is given by the followingequation:VO = VI (D/256)whereVO = analog output voltageVI = fixed input voltageD = digital input code converted to decimalIn voltage-mode operation, these devices meet the following specification:PARAMETERTEST CONDITIONSMINMAXUNITL inearity error at REFVDD = 5V,OUT1 = ,OUT2 at GND,TA = +25 C1 LSB SLAS061D SEPTEMBER 1986 REVISED JUNE 20076 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PRINCIPLES OF OPERATIONThe TLC7524C, TLC7524E, and TLC7524I are 8-Bit Multiplying DACs consisting of an inverted R-2R ladder,analog switches, and data input latches.

6 Binary-weighted currents are switched between the OUT1 and OUT2bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-orderbits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weightedcurrent sources. Most applications only require the addition of an external operational amplifier and a equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire referencecurrent, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through thetermination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to thesubstrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With alldigital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switchcapacitance (120pF maximum) appears at OUT1.

7 With all digital inputs low, the situation is reversed as shownin Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref wouldbe switched to DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR controlsignals. When CS and WR are both low, analog output on these devices responds to the data activity on theDB0 DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects theanalog output. When either the CS signal or WR signal goes high, the data on the DB0 DB7 inputs are latcheduntil the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the stateof the WR devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4.

8 Table 1 and Table 2 summarize inputcoding for unipolar and bipolar operation pF30 pFIIkgI/256 IIkgFigure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low SLAS061D SEPTEMBER 1986 REVISED JUNE 20077 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION+ OutputRA = 2 k (see Note A)WRCSDB0 DB7 VrefC (see Note B)RBVDDGNDOUT2 OUT1 RFBNOTES: A. RA and RB used only if gain adjustment is C phase compensation (10-15 pF) is required when using high-speed amplifiers to preventringing or 3. Unipolar Operation (2-Quadrant Multiplication)Output20 k 5 k 10 k 20 k ++ RFBOUT1 OUT2 GNDVDDRBC (see Note B)VrefDB0 DB7 CSWR(see Note A)RA = 2 k NOTES: A. RA and RB used only if gain adjustment is C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or 4. Bipolar Operation (4-Quadrant Operation)Table 1. Unipolar Binary CodeTable 2.

9 Bipolar (Offset Binary) CodeDIGITAL INPUT(see Note 3)ANALOG OUTPUTDIGITAL INPUT(see Note 4)ANALOG OUTPUTMSBLSBANALOG OUTPUTMSBLSBANALOG OUTPUT1 1 1 1 1 1 1 1 Vref (255/256)1 1 1 1 1 1 1 1 Vref (127/128)1 0 0 0 0 0 0 1 Vref (129/256)1 0 0 0 0 0 0 1 Vref (1/128)1 0 0 0 0 0 0 0 Vref (128/256) = Vref/21 0 0 0 0 0 0 000 1 1 1 1 1 1 1 Vref (127/256)0 1 1 1 1 1 1 1 Vref (1/128)0 0 0 0 0 0 0 1 Vref (1/256)0 0 0 0 0 0 0 1 Vref (127/128)0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 VrefNOTE 3: LSB = 1/256 (Vref)NOTE 4: LSB = 1/128 (Vref) SLAS061D SEPTEMBER 1986 REVISED JUNE 20078 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION microprocessor interfacesA0 A15Z 80AD0 D7 WRIORQA ddress BusDecodeLogicTLC7524 OUT2 OUT1 CSWRDB0 DB7 Data BusFigure 5. TLC7524: Z-80A InterfaceData BusDB0 DB7 WRCSOUT1 OUT2 TLC7524 DecodeLogicAddress BusVMA 2D0 D76800A0 A15 Figure 6. TLC7524: 6800 Interface SLAS061D SEPTEMBER 1986 REVISED JUNE 20079 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION microprocessor interfaces (continued)8-BitLatchAD0 AD78051A8 A15 ALEA dress/Data BusDecodeLogicTLC7524 OUT2 OUT1 CSWRDB0 DB7 Address BusWRFigure 7.

10 TLC7524: 8051 InterfaceRevision HistoryDATEREVPAGESECTIONDESCRIPTION6/07 DFront Page Deleted Available Options Inserted Package/Ordering :Page numbers for previous revisions may differ from page numbers in the current OPTION 1 PACKAGING INFORMATIONO rderable DeviceStatus(1)Package TypePackageDrawingPinsPackageQtyEco Plan(2)Lead/Ball Finish(6)MSL Peak Temp(3)Op Temp ( C)Device Marking(4/5)SamplesTLC7524 CDACTIVESOICD1640 Green (RoHS& no Sb/Br)CU NIPDAUL evel-1-260C-UNLIM0 to 70 TLC7524 CTLC7524 CDG4 ACTIVESOICD1640 Green (RoHS& no Sb/Br)CU NIPDAUL evel-1-260C-UNLIM0 to 70 TLC7524 CTLC7524 CDRACTIVESOICD162500 Green (RoHS& no Sb/Br)CU NIPDAUL evel-1-260C-UNLIM0 to 70 TLC7524 CTLC7524 CFNACTIVEPLCCFN2046 Green (RoHS& no Sb/Br)CU SNLevel-1-260C-UNLIM0 to 70 TLC7524 CTLC7524 CFNRACTIVEPLCCFN201000 Green (RoHS& no Sb/Br)CU SNLevel-1-260C-UNLIM0 to 70 TLC7524 CTLC7524 CNACTIVEPDIPN1625 Green (RoHS& no Sb/Br)CU NIPDAUN / A for Pkg Type0 to 70 TLC7524 CNTLC7524 CNE4 ACTIVEPDIPN1625 Green (RoHS& no Sb/Br)