RSL10 - Bluetooth 5 Radio System-on-Chip (SoC)

1 Semiconductor Components Industries, LLC, 2016 May, 2018 Rev. 31 Publication Order Number: RSL10 /DRSL10 Bluetooth ) 5 RadioSystem-on-Chip (SoC)IntroductionRSL10 is an ultra low power, highly flexible multi GHz Radio specifically designed for use in high performancewearable and medical applications. With its Arm Cortex M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth lowenergy technology and GHz proprietary protocol stacks, withoutsacrificing power Features Rx Sensitivity ( Bluetooth Low Energy Mode, 1 Mbps): 94 dBm Data Rate: to 2000 kbps Transmitting Power.

2 17 to +6 dBm Peak Rx Current = mA ( V VBAT) Peak Rx Current = mA (3 V VBAT) Peak Tx Current (0 dBm) = mA ( V VBAT) Peak Tx Current (0 dBm) = mA (3 V VBAT) Bluetooth 5 Certified with LE 2M PHY Support Arm Cortex M3 Processor Clocked at up to 48 MHz LPDSP32 for Audio Codec Supply Voltage Range: V Current Consumption ( V VBAT): Deep Sleep, IO Wake up: 50 nA Deep Sleep, 8 kB RAM Retention: 300 nA Audio Streaming at 7 kHz Audio BW: mA RX, mA TX Current Consumption (3 V VBAT): Deep Sleep, IO Wake up: 25 nA Deep Sleep, 8 kB RAM Retention: 100 nA Audio Streaming at 7 kHz Audio BW.

3 MA RX, mA TX 384 kB of Flash Memory Highly integrated System on Chip (SoC) Supports FOTA (Firmware Over The Air) UpdatesWLCSP51 CASE = Specific Device CodeA= Assembly LocationWL= Wafer LotY or YY = YearWW= Work WeekG or G= Pb Free PackageRSL10 AWLYYWWGD evicePackageShipping ORDERING INFORMATIONNCH RSL10 101WC51 ABGWLCSP51(Pb Free)5000 / Tape &Reel For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011 RSL10 101Q48 ABGQFN48(Pb Free)3000 / Tape &Reel481 QFN48 CASE 485BA(QFN48)(WLCSP51) Arm Cortex M3 Processor: A 32 bit core forreal time applications, specifically developed to enablehigh performance low cost platforms for a broad rangeof low power applications.

4 LPDSP32: A 32 bit Dual Harvard DSP core thatefficiently supports audio codecs required for wirelessaudio communication. Various codecs are available tocustomers through libraries that are included inRSL10 s development tools. Radio Frequency Front End: Based on a GHz RFtransceiver, the RFFE implements the physical layer ofthe Bluetooth low energy technology standard and otherproprietary or custom protocols. Protocol Baseband Hardware: Bluetooth 5 certifiedand includes support for a 2 Mbps RF link and customprotocol options. The RSL10 baseband stack issupplemented by support structures that enableimplementation of ON Semiconductor and customerdesigned custom protocols.

5 Highly Integrated SoC: The dual core architecture iscomplemented by high efficiency power managementunits, oscillators, flash and RAM memories, a DMAcontroller, along with a full complement of peripheralsand interfaces. Deep Sleep Mode: RSL10 can be put into a DeepSleep Mode when no operations are required. VariousDeep Sleep Mode configurations are available,including: IO wake up configuration. The powerconsumption in deep sleep mode is 50 nA ( VVBAT). Embedded 32 kHz oscillator running with interruptsfrom timer or external pin. The total current drain is90 nA ( V VBAT).

6 As above with 8 kB RAM data retention. The totalcurrent drain is 300 nA ( V VBAT). With the exception of IO wake up onlyconfiguration, the on chip buck converter can alsobe enabled to reduce current consumption in DeepSleep Mode (at higher VBAT voltages). Standby Mode: Can be used to reduce the averagepower consumption for off duty cycle operation,ranging typically from a few ms to a few hundreds ofms. The typical chip power consumption is 30 mA inStandby Mode. Multi Protocol Support: Using the flexibilityprovided by LPDSP32, the Arm Cortex M3 processor,and the RF front end; proprietary protocols and othercustom protocols are supported.

7 Flexible Supply Voltage: RSL10 integrates high efficiency power regulators and has a VBAT range to V. See Table 2. RECOMMENDEDOPERATING CONDITIONS. Highly Configurable Interfaces: I2C, UART, two SPIinterfaces, PCM interface, multiple GPIOs. It alsosupports a digital microphone interface (DMIC) and anoutput driver (OD). The Asynchronous Sample Rate Converter (ASRC)Block and Audio Sink Clock Blocks Provides a meansof synchronizing the audio sample rate between anaudio source and an audio sink. The audio sink clockalso provides a high accuracy mechanism to measure aninput clock used for the RTC or protocol timing.

8 Flexible Clocking Scheme: RSL10 must be clockedfrom the XTAL/PLL of the Radio front end at 48 MHzwhen transmitting or receiving RF traffic. When RSL10is not transmitting/receiving RF traffic, it can run offthe 48 MHz XTAL, the internal RC oscillators, the32 kHz oscillator, or an external clock. A lowfrequency RTC clock at 32 kHz can also be used inDeep Sleep Mode. It can be sourced from either theinternal XTAL, the RC oscillator, or a digital input pad. Diverse Memory Architecture: 76 kB of SRAM program memory and 88 kB of SRAM data memoryare available. A total of 384 kB of flash is available tostore the Bluetooth stack and other applications.

9 TheArm Cortex M3 processor can execute from SRAMand/or flash. IP Protection Feature: Ensures that the customer sflash contents cannot be copied by a third party. Itprevents any core or memory from being accessedexternally after the chip has booted. Ultra Low Power Consumption ApplicationExamples: Audio Signal Streaming: IDD = mA @ V in Rx Mode for receiving, decoding andsending an 7 kHz bandwidth audio signal to the SPIinterface using a proprietary custom audio protocolfrom ON Semiconductor. Low Duty Cycle Advertising: IDD mA foradvertising at all three channels at 5 second intervals@ VBAT 3 V, DCDC converter enabled.

10 RoHS Compliant INTERNAL BLOCK DIAGRAMThe block diagram of the RSL10 chip is shown in Figure PHYB aseband controllerBluetooth 5 (LE 2M) and custom protocolPower ManagementLPDSP3232 bit Dual Harvard coreArm[ Cortex[-M3 ProcessorInterfacesOscillatorsTimersIP ProtectionJTAGSWJ DPDMARAMs andFlashADCPCMI2 CUARTADC (4x)DMIC(2x)PWM(2x)GPIOXTAL_32 kHzXTAL_48 MHzBatteryODSPI(2x)BusArbitersSample Rate ConverterAudio Sink ClockCountersFigure 1. RSL10 Block DiagramTable 1. ABSOLUTE MAXIMUM RATINGSS ymbolParameterMinMaxUnitVBATP ower supply voltage supply voltage front end ground VVSSAA nalog ground VVSSDD igital core and I/O ground VVinVoltage at any input pinVSSD + functionalFunctional temperature range 4085 CT storageStorage temperature range 4085 CCaution: Class 2 ESD Sensitivity, JESD22 A114 B (2000 V)The QFN package meets 450 V CDM levelStresses exceeding those listed in the Maximum Ratings table may damage the device.]]