NCP81075 - Dual MOSFET Gate Driver, High Performance

1 DATA Semiconductor Components Industries, LLC, 2016 February, 2022 Rev. 41 Publication Order Number: NCP81075 /D Dual MOSFET Gate Driver, High PerformanceNCP81075 IntroductionThe NCP81075 is a high Performance dual MOSFET gate driveroptimized to drive the gates of both high and low side powerMOSFETs in a synchronous buck converter . The NCP81075 uses anon chip bootstrap diode to eliminate the external discrete diode. Ahigh floating top driver design can accommodate HB voltage as highas 180 V. The low side and high side are independently controlledand match to 4 ns between the turn on and turn off of each Under Voltage lockout is provided for the high side andlow side driver forcing the output low when the drive voltage is belowa specific Drives Two N-Channel MOSFETs in High-Side and Low-SideConfiguration Floating Top Driver Accommodates Boost Voltage up to 180 V Switching Frequency up to 1 MHz 20 ns Propagation Delay Times 4 A Sink, 4 A Source Output Currents 8 ns Rise / 7 ns Fall Times with 1000 pF Load UVLO Protection Specified from 40 C to 140 C Offered in SOIC 8 (D), DFN8 (MN), WDFN10 (MT)

2 Packages These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantApplications Telecom and Datacom Isolated Non Isolated Power Supply Architectures Class D Audio Amplifiers Two Switch and Active Clamp Forward ConvertersSimplified Application DiagramVSSVDDHILIVDDHBHOHSLOVINVOUTNCP81 075 PWMCONTROLLERD evicePackageShipping ORDERING INFORMATIONMARKING DIAGRAMSSOIC 8 NBCASE 751 07 For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011 (Pb Free) NCP81075 MNTXGDFN8(Pb Free)4000 /Tape & ReelNCP81075 MTTXGWDFN10(Pb Free)4000 /Tape & Reel2500 /Tape & ReelPINOUT DIAGRAMSDFN8 CASE 506 CYWDFN10 CASE 511CE1 NCP81075 = Specific Device CodeA= Assembly LocationL= Wafer LotY= YearW= Work WeekG= Pb Free PackageNCP81075 ALYWGG(Note: Microdot may be in either location)1 NCP81075 ALYWGG18181 NCP81075 (top views) 1.

3 PIN DESCRIPTIONPin Supply to the Lower Gate Driver22 HBHigh Side Bootstrap Supply33 HOHigh Side Output44 HSHigh Side Source57 HIHigh Side Input68 LILow Side Input79 VSSN egative Supply Return810 LOLow Side Output 5,6 NCNo ConnectTable 2. MAXIMUM RATINGSP arameterValueUnitsVDD to 24 VVHB to 200 VVHODCVHS to VHB + Pulse < 100 nsVHS 2 to VHB + , (VHB VHS < 24)VHSDC 20 to 200 VDDVVLODC to VDD + pulse < 100 ns 2 to VDD + , VLI 10 to 24 VVHB HS to 24 VOperating Junction Temperature Range, TJ 40 to 170 CStorage Temperature, TSTG 65 to 150 CLead Temperature (Soldering, 10 sec)+300 CHBM1000 VCDM2000 VStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be VHB VHS should be in the range of V to +20 3.

4 RECOMMENDED OPERATING CONDITIONSP arameterMinNomMaxUnitsVDDS upply Voltage on HS (DC) 10180 VDDVHBV oltage on HBVHS + 8,VDD 1 VHS + 20,180 Voltage Slew Rate on HS50V / nsTJOperating Junction Temperature Range 40+140 CVHOVHS + + operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device MAXIMUM RATINGST able 4. ELECTRICAL/THERMAL INFORMATION (All signals referenced to GND unless noted otherwise, Note 2)Thermal CharacteristicSOICDFN8 DFN10 UnitqJA Junction to Ambient thermal resistance1163635 C/WqJC(top) Junction to case (Top) thermal resistance984232qJB Junction to Board thermal (Bottom) Junction to case (Bottom) thermal Junction to top characterization Junction to board characterization Sensitivity Level (MSL)QFN Package12.

5 This data was taken using the JEDEC proposed High K Test 5. ELECTRICAL CHARACTERISTICSU nless otherwise stated: TA = TJ = 40 C to 140 C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HOParameterTest ConditionMinTypMaxUnitsSUPPLY CURRENTSIDDVDD quiescent currentVLI = VHI = operating currentf = 500 kHz, CLOAD = = 300 kHz, CLOAD = voltage quiescent currentVLI = VHI = 0 voltage operating currentf = 500 kHz, CLOAD = = 300 kHz, CLOAD = to VSS quiescent currentVHS = VHB = 110 to VSS operating currentf = 500 kHz, CLOAD = , VLIHI nput rising , VLILI nput falling Pulldown Resistance100170350kWUNDERVOLTAGE PROTECTION (UVLO)VDD rising threshold rising threshold DIODEVFLow current forward voltageI VDD HB = 100 current forward voltageI VDD HB = 100 resistance, DVF/DII VDD HB = 100 mA and 80 GATE DRIVERVLOLLow level output voltageILO = 100 level output voltageILO = 100 mA, VLOH = VDD pull up currentVLO = 0 V4 APeak pull down currentVLO = 12 5.

6 ELECTRICAL CHARACTERISTICSU nless otherwise stated: TA = TJ = 40 C to 140 C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HOParameterUnitsMaxTypMinTest ConditionHO GATE DRIVERVHOLLow level output voltageIHO = 100 level output voltageIHO = 100 mA, VHOH = VHB pull up currentVLO = 0 V4 APeak pull down currentVLO = 12 V4 PROPAGATION DELAYStDLFFVLI falling to VLO fallingCLOAD = 0 ( 40 to 125 C)2045nsCLOAD = 0 ( 40 to 140 C)2050tDHFFVHI falling to VHO fallingCLOAD = 0 ( 40 to 125 C)2045 CLOAD = 0 ( 40 to 140 C)2050tDLRRVLI rising to VLO risingCLOAD = 0 ( 40 to 125 C)2045 CLOAD = 0 ( 40 to 140 C)2050tDHRRVHI rising to VHO risingCLOAD = 0 ( 40 to 125 C)2045 CLOAD = 0 ( 40 to 140 C)2050 DELAY MATCHINGtMONLI ON, HI OFF, HI RISE AND FALL TIMEtRLO, HOCLOAD = 1000 pF8nstFLO, HOCLOAD = 1000 pF7tRLO, HO (3 V to 9 V)CLOAD = , HO (3 V to 9 V)

7 CLOAD = input pulse width thatchanges the output30nst2 Bootstrap diode turn off timeIF = 100 mA, IREV = 100 mA(Notes 3 and 4)50 Product parametric Performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different Typical values for TA = 25 C4. IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap Block DiagramFigure 1. Internal Block DiagramTiming DiagramsFigure 2. UVLOD elay ~ 40usUVLOT hresholdsLILOHIHOVDD / VHB-VHSD elay ~ 40usNote: If HI is set and the High Side driver (VHB VHS) crosses its UVLO threshold100ns after the VDD UVLO then a rising edge on HI is required to pull HO 3. TMON and TMOFFLOHIHOLITMOFFTON10%90%10%90%TDLRRTD HRRTDLFFTDHFFHI, LIHO, LOFigure 4.

8 Propagation DelaysLOGIC DIAGRAMSF igure 5. NCP81075 Top ViewWDFN10 LOVSSLIHIGNDPad123410987 VDDHBHOHSNC56 NCSOIC 8 LOVSSLIHI12348765 VDDHBHOHSNote: The VSS Pin and the GND Pad are internally CHARACTERISTICSF igure 6. Delay Matching vs. TemperatureFigure 7. Quiescent Current vs. SupplyVoltage HighTEMPERATURE ( C)SUPPLY VOLTAGE (V)1251007550250 25 50 5 4 3 8. Quiescent Current vs. SupplyVoltage LowFigure 9. Input Threshold vs. TemperatureSUPPLY VOLTAGE (V)TEMPERATURE ( C) 25 10. Input Threshold vs. Supply VoltageFigure 11. Output Current vs. Output VoltageSUPPLY VOLTAGE (V)OUTPUT VOLTAGE (V) MATCHING (ns)QUIESCENT CURRENT (mA)QUIESCENT CURRENT (mA)HI, LI (V)INPUT THRESHOLD (V)OUTPUT CURRENT (A)150 CurrentI(HB) (VDD)I(HB) = 25 CurrentSource CurrentHI ; LI = GNDHI ; LI = CHARACTERISTICSF igure 12.

9 Propagation Delay vs. SupplyVoltageFigure 13. Propagation Delay vs. TemperatureSUPPLY VOLTAGE (V)TEMPERATURE ( C) 25 500510152025 Figure 14. Operating Current vs. FrequencyFigure 15. Diode Current vs. Diode VoltageFREQUENCY (kHz)DIODE VOLTAGE (V) DELAY (ns)PROPAGATION DELAY (ns)OPERATING CURRENT (mA)DIODE CURRENT (mA)22 FallingRising125 Falling EdgeRising Edge5108101010841I(VDD)I(HB) INFORMATIONThe NCP81075 is a high Performance dual MOSFET gatedriver optimized for driving the gates of both high side andlow side power MOSFETs in a synchronous buck convertertopology. A high and a Low input signals are all that isrequired to properly drive the high side and low Side DriverThe low side driver is designed to drive low RDSONN channel MOSFETs. The typical output resistances for thedriver are ohms for sourcing and 1 ohm for sinking gatecurrent.

10 Due to the parasitic inductances of the packages,drive circuits and the nonlinearity of the MOSFETs outputresistances the recorded peak current is close to 4 low output resistances allow the driver to have 8 nsrise and 7 ns fall times into a 1 nF load. When the driver isenabled, the driver s output is in phase with LI. When theNCP81075 is disabled, the low side gate is held Side DriverThe high side driver is designed to drive a floating lowRDSON N channel MOSFET . The output resistances for thedriver are ohms for sourcing and 1 ohm for sinking gatecurrent. The bias voltage for the high side driver is realizedby an external bootstrap supply circuit which is connectedbetween the HB and HS bootstrap circuit is comprised of only the bootstrapcapacitor since the bootstrap diode is internal.